1. Field of Art
The disclosure generally relates to the field of static timing analysis. More specifically, the disclosure relates to performing hierarchical static timing analysis.
2. Description of the Related Art
The amount of runtime and memory used to perform flat static timing analysis in electronic design automation software has significantly increased as designs have become more complex. Hierarchical static timing analysis (HSTA) is increasingly used to reduce peak memory and runtime by up to an order of magnitude or more. Clock re-convergence pessimism removal (CRPR) is used in flat static timing analysis to improve calculations and produce more accurate timing data. CRPR can identify common points in a clock network to improve the amount of slack for a timing path between two latches when the clock pins of the two latches are communicatively coupled to a common point. This reduces unnecessarily pessimistic timing calculations. However, performing CRPR in HSTA has proven difficult due to dependence on not only clock timing, but clock topology as well. In HSTA, some clock paths travel between multiple blocks or hierarchies. This means that the complete clock network cannot be seen during any single level of analysis since the clock network can traverse multiple hierarchies. Thus, conventional block level analysis is unable to provide accurate clock re-convergence pessimism (CRP) values when a common point is located in another block or hierarchy. HSTA also should accurately analyze different types of CRP values including static CRP, dynamic CRP, and various CRP modes such as muxed-CRP removal, same transition mode and statistical mode.